Design of Low-Power Specific Parallel Array Multipliers
نویسندگان
چکیده
JCHPS Special Issue 8: December 2016 www.jchps.com Page 9 Design of Low-Power Specific Parallel Array Multipliers C Vivek*, R. Subalakshmi Department of Electronics and Communication Engineering, M. Kumarasamy College of Engineering, Karur, Tamil Nadu. *Corresponding author: E-Mail: [email protected] ABSTRACT Multipliers play a critical part in recent digitalized life. In this advanced sphere, many investigation are going to propose multipliers with high speed rate, less power utilization or periodic arrangement and small size. Integration of them in a single multiplier allows to use for applications with less competence, high speed rate and dense VLSI application. The common multiplication method is "add and shift" algorithm. In this paper various low power multiplier design techniques are analyzed which includes selective activation approach, DCT flow graph algorithm, multiplier less design in FPGA, 2-signed 2 dimensional bypassing array multiplier, column bypassing multiplier and so on.
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